QuartusII使用教程

module top( input data_in, input clk, input rst, output reg [7:0] reg_vec, output reg [7:0] reg_loop, output reg data_out_vec, output  reg data_out_loop ); integer loop; always@(posedge clk) begin
    if(rst==1'b0)
    begin reg_vec<=8'h00;
        data_out_vec<=1'b0;
    end
    else
    begin reg_vec[0]<=data_in;        //s1
        reg_vec[1]<=reg_vec[0];     //s2
        reg_vec[2]<=reg_vec[1];     //s3
        reg_vec[3]<=reg_vec[2];     //s4
        reg_vec[4]<=reg_vec[3];     //s5
        reg_vec[5]<=reg_vec[4];     //s6
        reg_vec[6]<=reg_vec[5];     //s7
        reg_vec[7]<=reg_vec[6];     //s8
        data_out_vec<=reg_vec[7];   //s9
    end
end

always@(posedge clk) begin
    if(rst==1'b0)
    begin reg_loop<=8'h00;
        data_out_loop<=1'b0;
    end
    else
    begin reg_loop[0]<=data_in;                    //s10
        for(loop=0;loop<=6;loop=loop+1)          //s11
            reg_loop[loop+1]<=reg_loop[loop];     //s12
           data_out_loop<=reg_loop[7];              //s13
    end
end
endmodule